We seem to be getting a trickle of news regarding the latest CPUs from AMD each week.

The latest information comes following an investor presentation, where AMD confirmed that their 3rd Generation Ryzen and Ryzen Threadripper processors will be launching this year. AMD also announced that they will be launching the 2nd Generation Ryzen Pro mobile products for notebooks this spring. AMD’s codenamed Rome processors for servers are also due in 2019, but the manufacturer does not elaborate about their exact timing.

No date was mentioned regarding the new Zen 2 Ryzen 3000 but the news backs up previous rumours of a 7/7/2019 release, with the data a nod to the 7nm fabrication process.

While it was expected that the Ryzen 3000 will be arriving mid-year, less has been said about the new Threadripper chips.

Not much was said about the CPU specifications, with the Threadripper parts we know that they share a lot of features of the 2nd Gen EPYC (codenamed Rome) server CPUs. These have eight 7nm Zen 2-based chiplets to provide up to 64 cores and an IO die. The big difference with the previous generation was that Threadripper only offered half the number of cores that EPYC had.

With AMD’s 3rd Gen Ryzen processors based on the Zen 2 microarchitecture, we know quite a bit of information already, though some of it is through leaks and not 100% confirmed. The biggest difference is the massive core count increase, with the top of the range Ryzen 9 3850X offering 16 cores with 32 threads. Lower end options have all been upgraded with the Ryzen 7 models now featuring 12-cores, and Ryzen 5 now being 8-cores. Even the lower end Ryzen 3 3300 will feature 6-cores.

With the Ryzen desktop chips going up to 16-cores it likely that these chips will start eating into the HEDT Threadripper market so it will be interesting to see how far AMD will push their Threadripper models to differentiate them.

The new generation of Ryzen CPUs, and presumably Threadripper will also introduce PCIe 4.0 on AMD X570 motherboards. This doubles the available bandwidth for the PCIe lanes.

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