Ok so I am planning on doing a couple of posts about the new Nvidia 8800 GT Graphics Processor, and the new Intel Core 2 Extreme QX9650. Two of the important features of these products is the reduction in Fabrication process size. The Intel Core 2 Extreme QX9650 has moved to the 45nm Fabrication process from 65nm and the Nvidia 8800 GT has moved from the 90nm Fabrication Process to 65nm. So the reason for this post is what the hell is the Fabrication Process and why is it good for our CPUs/GPUs?
The simple answer is that the smaller the fabrication processes then the more transistors you can fit on each chip, and the more transistors you have the faster the technology you are producing can run. The other advantage is that shrinking a 65-nanometre design to 45-nanometres would result in a die that is less than half the size allowing a manufacturer to reduce the power consumption and heat dissipation of the chip
In fact in 1965 Gordon Moore stated that the rate that the number of transistors that can be inexpensively placed on an integrated circuit will double every two years.
“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year … Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer.” Moore, Gordon E. (1965). Cramming more components onto integrated circuits. Electronics Magazine
In fact this theory extended much further than the original 10 years Moore predicted, with the law not expected to end for possibly over a decade further.
When the paper first came out, chips sported about 60 distinct devices. In contrast, Intel's latest Core 2 Extreme QX9650 chip is comprised of approximately 410 Million transistors.
The end of Moore's Law will not be due to the limitations of the companies developing the integrated circuits but the limitations of physics (dam you physics!). On April 13, 2005, Gordon Moore himself stated:
“In terms of size [of transistor] you can see that we're approaching the size of atoms which is a fundamental barrier, but it'll be two or three generations before we get that far—but that's as far out as we've ever been able to see. We have another 10 to 20 years before we reach a fundamental limit. By then they'll be able to make bigger chips and have transistor budgets in the billions.”
If companies manage to develop the technologies the smallest possible transistor gate size will be around 4-nanometer which will use a 16-nanometer technology process. When you start to go smaller than this tunnelling will begin to occur, where electrons will simply pass through the channel(gate) on their own due to the source (where electrons come from) and the drain (where they go) will be extremely close. When that happens, transistors will lose their reliability, because it will be impossible to control the flow of electrons and hence the creation of 1s and 0s. By conservative estimates the 16 nm technology is expected to be reached by semiconductor companies in the 2018 timeframe.
Even though we know it should be possible to reduce transistor size down to the 16-nanometer technology process. It is becoming increasingly difficult to manufacture the smaller transistor sizes in fact one of the major technological roadblocks has been the transition from 65nm to 45nm process. The way an electric field behaves inside silicon dioxide (dielectric) causes to much gate leakage current and therefore an alternative is needed. For the 45 nm process Intel will be using high-k and metal gate materials, which Intel considers to be a fundamental change in transistor design. While the specific high-k and metal gate materials have not been disclosed for the new 45nm Intel chips it is likely they are based on hafnium compounds (e.g. hafnium oxide or hafnium silicate).
The main benefits of this technology in the Intel chip is a 20 percent faster switching speed in the same power envelope and a 30 percent power reduction at the transistor level. Intel has three 45nm Fabs – one in Oregon, one in Arizona and a third in Israel.
It expected that AMD will release chips based on the 45nm Fabrication Process in late 2008, with delays this could be set back to 2009. AMD will also be planning on staying with silicon dioxide until the 32nm Fabrication Process.
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